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/**************************************************************************//** * @file main.c * @version V3.00 * $Revision: 2 $ * $Date: 15/09/02 10:03a $ * @brief Demonstrate how to set GPIO pin mode and use pin data input/output control. * @note * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved. * ******************************************************************************/#include "stdio.h"#include "M451Series.h"#include "NuEdu-Basic01.h"
#define PLL_CLOCK 72000000
void SYS_Init(void){ /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/
/* Enable HIRC clock (Internal RC 22.1184MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
/* Wait for HIRC clock ready */ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Select HCLK clock source as HIRC and and HCLK clock divider as 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
/* Enable HXT clock (external XTAL 12MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
/* Wait for HXT clock ready */
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
/* Set core clock as PLL_CLOCK from PLL */ CLK_SetCoreClock(PLL_CLOCK);
/* Enable UART module clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Select UART module clock source as HXT and UART module clock divider as 1 */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1));
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PD multi-function pins for UART0 RXD(PD.6) and TXD(PD.1) */ SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD6MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk); SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD6MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD);
}
void UART0_Init(){ /*---------------------------------------------------------------------------------------------------------*/ /* Init UART */ /*---------------------------------------------------------------------------------------------------------*/ /* Reset UART module */ SYS_ResetModule(UART0_RST);
/* Configure UART0 and set UART0 baud rate */
UART_Open(UART0, 115200);
}
/*---------------------------------------------------------------------------------------------------------*//* Main Function *//*---------------------------------------------------------------------------------------------------------*/int32_t main(void){ uint32_t temp,temp1 = 0; /* Unlock protected registers */ SYS_UnlockReg();
/* Init System, peripheral clock and multi-function I/O */
SYS_Init();
/* Lock protected registers */ SYS_LockReg();
/* Init UART0 for printf */
UART0_Init();
printf("\nNuEdu-SDK-M451 PWM-DAC\n");
Initial_PWM_LED();
Initial_PWM_DAC();
Initial_LED();
Open_ADC_Knob();
Write_PWMDAC(1,temp1);
while(1)
{
//Get Volume Knob Data
temp = Get_ADC_PWMDAC(); //Volume Range: 0 ~ 4095
Write_LED_Bar((temp * (8 + 1) / 4096));
Write_PWMDAC(1,temp1++);
if(temp1>100)
temp1 = 0;
CLK_SysTickDelay(10000);
}
}
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#include <stdio.h> #include "M451Series.h" #include "NuEdu-Basic01_PWMDAC.h" void Write_PWMDAC(unsigned char Enable, unsigned char ch0_dut) { /* set PWMB channel 0 output configuration */ PWM_ConfigOutputChannel(PWM1, 4, 1000, ch0_dut); // Start PWM COUNT PWM_Start(PWM1, 1 << 4); if(Enable == 0) /* Enable PWM Output path for PWMB channel 0 */ PWM_DisableOutput(PWM1, 1 << 4); else /* Diable PWM Output path for PWMB channel 0 */ PWM_EnableOutput(PWM1, 1 << 4); } void Initial_PWM_DAC(void) { GPIO_SetMode(PC, BIT13, GPIO_MODE_INPUT); //avoid to pwm dac out SYS->GPC_MFPH &= ~SYS_GPC_MFPH_PC13MFP_Msk ; SYS->GPC_MFPH |= SYS_GPC_MFPH_PC13MFP_PWM1_CH4; /* Enable PWM module clock */ CLK_EnableModuleClock(PWM1_MODULE); /* Select PWM module clock source */ CLK_SetModuleClock(PWM1_MODULE, CLK_CLKSEL2_PWM1SEL_PCLK1, 0); /* Reset PWM1 channel 0~5 */ SYS_ResetModule(PWM1_RST); }
/**************************************************************************//** * @file NuEdu-NuEdu-Basic01_RGBLED.c * @version V1.00 * $Revision: 5 $ * $Date: 15/09/02 10:02a $ * @brief NuEdu-Basic01_RGBLED driver source file for NuEdu-SDK-M451 * * @note * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved. *****************************************************************************/ #include <stdio.h> #include "M451Series.h" #include "NuEdu-Basic01_RGBLED.h" /** @addtogroup M451_Library M451 Library @{ */ /** @addtogroup NuEdu-SDK-M451_Basic01 M451_Basic01 Library @{ */ /** @addtogroup M451_Basic01_FUNCTIONS RGB LED Functions @{ */ /** * @brief Set multi-function pins for PWM1 channel 0,1,2 * @return None */ void Initial_PWM_LED(void) { /* Set PC9~PC11 multi-function pins for PWM1 Channel0~2 */ SYS->GPC_MFPH &= ~(SYS_GPC_MFPH_PC9MFP_Msk | SYS_GPC_MFPH_PC10MFP_Msk | SYS_GPC_MFPH_PC11MFP_Msk); SYS->GPC_MFPH |= SYS_GPC_MFPH_PC9MFP_PWM1_CH0 | SYS_GPC_MFPH_PC10MFP_PWM1_CH1 | SYS_GPC_MFPH_PC11MFP_PWM1_CH2; /* Enable PWM module clock */ CLK_EnableModuleClock(PWM1_MODULE); /* Select PWM module clock source */ CLK_SetModuleClock(PWM1_MODULE, CLK_CLKSEL2_PWM1SEL_PCLK1, 0); /* Reset PWM1 channel 0~5 */ SYS_ResetModule(PWM1_RST); } /** * @brief Set PWM clock enable and HCLK as PWM clock source, * * @param[in] ch Channel numbers that will be enabled. * * @param[in] ch0_fre Channel 0 frequency. * * @param[in] ch0_dut Channel 0 duty. * * @param[in] ch1_fre Channel 1 frequency. * * @param[in] ch1_dut Channel 1 duty. * * @param[in] ch2_fre Channel 2 frequency. * * @param[in] ch2_dut Channel 2 duty. * * @return None */ void PWM_LED(unsigned char ch, unsigned int ch0_fre, unsigned int ch0_dut, unsigned int ch1_fre, unsigned int ch1_dut, unsigned int ch2_fre, unsigned int ch2_dut) { /* set PWMA channel 1 output configuration */ PWM_ConfigOutputChannel(PWM1, 0, ch0_fre, ch0_dut); PWM_ConfigOutputChannel(PWM1, 1, ch1_fre, ch1_dut); PWM_ConfigOutputChannel(PWM1, 2, ch2_fre, ch2_dut); /* Enable PWM Output path for PWMA channel 0 */ PWM_EnableOutput(PWM1, ch); // Start PWM_Start(PWM1, ch); } /*@}*/ /* end of group M451_Basic01_FUNCTIONS */ /*@}*/ /* end of group NuEdu-SDK-M451_Basic01 */ /*@}*/ /* end of group M451_Library */ /*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. **/
uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge) { uint32_t u32Src; uint32_t u32PWMClockSrc; uint32_t u32NearestUnitTimeNsec; uint16_t u16Prescale = 1, u16CNR = 0xFFFF; if(pwm == PWM0) u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM0SEL_Msk; else//(pwm == PWM1) u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM1SEL_Msk; if(u32Src == 0) { //clock source is from PLL clock u32PWMClockSrc = CLK_GetPLLClockFreq(); } else { //clock source is from PCLK SystemCoreClockUpdate(); u32PWMClockSrc = SystemCoreClock; } u32PWMClockSrc /= 1000; for(u16Prescale = 1; u16Prescale <= 0x1000; u16Prescale++) { u32NearestUnitTimeNsec = (1000000 * u16Prescale) / u32PWMClockSrc; if(u32NearestUnitTimeNsec < u32UnitTimeNsec) { if(u16Prescale == 0x1000) //limit to the maximum unit time(nano second) break; if(!((1000000 * (u16Prescale + 1) > (u32NearestUnitTimeNsec * u32PWMClockSrc)))) break; continue; } break; } // convert to real register value // every two channels share a prescaler PWM_SET_PRESCALER(pwm, u32ChannelNum, --u16Prescale); // set PWM to down count type(edge aligned) (pwm)->CTL1 = ((pwm)->CTL1 & ~(PWM_CTL1_CNTTYPE0_Msk << (2 * u32ChannelNum))) | (1UL << (2 * u32ChannelNum)); // set PWM to auto-reload mode (pwm)->CTL1 &= ~(PWM_CTL1_CNTMODE0_Msk << u32ChannelNum); PWM_SET_CNR(pwm, u32ChannelNum, u16CNR); return (u32NearestUnitTimeNsec); } /** * @brief This function Configure PWM generator and get the nearest frequency in edge aligned auto-reload mode * @param[in] pwm The pointer of the specified PWM module * - PWM0 : PWM Group 0 * - PWM1 : PWM Group 1 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 * @param[in] u32Frequency Target generator frequency * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%... * @return Nearest frequency clock in nano second * @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure PWM frequency may affect * existing frequency of other channel. */ uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle) { uint32_t u32Src; uint32_t u32PWMClockSrc; uint32_t i; uint16_t u16Prescale = 1, u16CNR = 0xFFFF; if(pwm == PWM0) u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM0SEL_Msk; else//(pwm == PWM1) u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM1SEL_Msk; if(u32Src == 0) { //clock source is from PLL clock u32PWMClockSrc = CLK_GetPLLClockFreq(); } else { //clock source is from PCLK SystemCoreClockUpdate(); u32PWMClockSrc = SystemCoreClock; } for(u16Prescale = 1; u16Prescale < 0xFFF; u16Prescale++)//prescale could be 0~0xFFF { i = (u32PWMClockSrc / u32Frequency) / u16Prescale; // If target value is larger than CNR, need to use a larger prescaler if(i > (0x10000)) continue; u16CNR = i; break; } // Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register i = u32PWMClockSrc / (u16Prescale * u16CNR); // convert to real register value // every two channels share a prescaler PWM_SET_PRESCALER(pwm, u32ChannelNum, --u16Prescale); // set PWM to down count type(edge aligned) (pwm)->CTL1 = ((pwm)->CTL1 & ~(PWM_CTL1_CNTTYPE0_Msk << (2 * u32ChannelNum))) | (1UL << (2 * u32ChannelNum)); // set PWM to auto-reload mode (pwm)->CTL1 &= ~(PWM_CTL1_CNTMODE0_Msk << u32ChannelNum); PWM_SET_CNR(pwm, u32ChannelNum, --u16CNR); if(u32DutyCycle) { PWM_SET_CMR(pwm, u32ChannelNum, u32DutyCycle * (u16CNR + 1) / 100 - 1); (pwm)->WGCTL0 &= ~((PWM_WGCTL0_PRDPCTL0_Msk | PWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum * 2)); (pwm)->WGCTL0 |= (PWM_OUTPUT_LOW << (u32ChannelNum * 2 + PWM_WGCTL0_PRDPCTL0_Pos)); (pwm)->WGCTL1 &= ~((PWM_WGCTL1_CMPDCTL0_Msk | PWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum * 2)); (pwm)->WGCTL1 |= (PWM_OUTPUT_HIGH << (u32ChannelNum * 2 + PWM_WGCTL1_CMPDCTL0_Pos)); } else { PWM_SET_CMR(pwm, u32ChannelNum, 0); (pwm)->WGCTL0 &= ~((PWM_WGCTL0_PRDPCTL0_Msk | PWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum * 2)); (pwm)->WGCTL0 |= (PWM_OUTPUT_LOW << (u32ChannelNum * 2 + PWM_WGCTL0_ZPCTL0_Pos)); (pwm)->WGCTL1 &= ~((PWM_WGCTL1_CMPDCTL0_Msk | PWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum * 2)); (pwm)->WGCTL1 |= (PWM_OUTPUT_HIGH << (u32ChannelNum * 2 + PWM_WGCTL1_CMPDCTL0_Pos)); } return(i); } /** * @brief Start PWM module * @param[in] pwm The pointer of the specified PWM module * - PWM0 : PWM Group 0 * - PWM1 : PWM Group 1 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. * Bit 0 is channel 0, bit 1 is channel 1... * @return None * @details This function is used to start PWM module. */ void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask) { (pwm)->CNTEN |= u32ChannelMask; }
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